View M93S56_1960657.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

m93s66, M93S56, m93s46 4k/2k/1k (x16) serial microwire bus eeprom with block protection preliminary data september 1998 1/24 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. ai02020 d v cc m93sx6 v ss c q pre w s figure 1. logic diagram industry standard microwire bus 1 million erase/write cycles, with 40 years data retention single organization by word (x16) word and entire memory programming instructions self-timed programming cycle with auto-erase ready/busy signal during programming single supply voltage: C 4.5v to 5.5v for m93sx6 version C 2.5v to 5.5v for m93sx6-w version C 1.8v to 5.5v for m93sx6-r version user defined write protected area page write mode (4 words) sequential read operation 5ms typical programming time enhanced esd and latch-up performances description this m93s46/s56/s66 specification covers a range of 4k/2k/1k bit serial eeprom products respectively. in this text, products are referred to as m93sx6. the m93sx6 is an electrically erasable programmable memory (eeprom) fabricated with stmicroelectronics high endurance single polysilicon cmos technology. s chip select input d serial data input q serial data output c serial clock pre protect enable w write enable v cc supply voltage v ss ground table 1. signal names 8 1 so8 (mn) 150mil width 8 1 psdip8 (bn) 0.25mm frame
the m93sx6 memory is accessed through a serial input (d) and output (q) using the microwire bus protocol. the m93sx6 is specified at 5v 10%, the m93sx6-w specified at 2.5v to 5.5v and the m93sx6-r specified at 1.8v to 5.5v. the m93s66/s56/s46 memory is divided into 256/128/64 x16 bit words respectively. these memory devices are available in both psdip8 and so8 package. the m93sx6 memory is accessed by a set of instructions which includes read, write, page write, write all and instructions used to set the memory protection. a read instruction loads the v ss q w pre c sv cc d ai02021 m93sx6 1 2 3 4 8 7 6 5 figure 2a. dip pin connections 1 v ss q w pre c sv cc d ai02022 m93sx6 2 3 4 8 7 6 5 figure 2b. so pin connections description (contd) symbol parameter value unit t a ambient operating temperature C40 to 125 c t stg storage temperature C65 to 150 c t lead lead temperature, soldering (so8 package) (psdip8 package) 40 sec 10 sec 215 260 c v io input or output voltages (q = v oh or hi-z) C0.3 to v cc +0.5 v v cc supply voltage C0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) (2) 7000 v electrostatic discharge voltage (machine model) (3) 1000 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and oth er relevant quality documents. 2. mil-std-883c, 3015.7 (100pf, 1500 w ). 3. eiaj ic-121 (condition c) (200pf, 0 w ). table 2. absolute maximum ratings (1) address of the first word to be read into an internal address pointer. the data contained at this address is then clocked out serially. the address pointer is automatically incremented after the data is output and, if the chip select input (s) is held high, the m93sx6 can output a sequential stream of data words. in this way, the memory can be read as a data stream from 16 to 4096 bits (for the m93s66), or continuously as the address counter automat- ically rolls over to 00 when the highest address is reached. within the time required by a program- ming cycle (t w ), up to 4 words may be written with help of the page write instruction. the whole mem- ory may also be erased, or set to a predetermined pattern, by using the write all instruction. 2/24 m93s66, M93S56, m93s46
ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc figure 3. ac testing input output waveforms symbol parameter test condition min max unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 5 pf note: 1. sampled only, not 100% tested. table 4. capacitance (1) (t a = 25 c, f = 1 mhz ) input rise and fall times 20ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc table 3. ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc , q in hi-z 1 m a i cc supply current (read) v cc = 5v, s = v ih , f = 1 mhz 1 ma supply current (write, erase) v cc = 5v, s = v ih , f = 1 mhz 2 ma i cc1 supply current (standby) v cc = 5v, s = v ss , c = v ss , w = v ss or v cc , pre = v ss or v cc 40 m a v il input low voltage (d, c, s, w, pre) C0.3 0.8 v v ih input high voltage (d, c, s, w, pre) 2v cc + 1 v v ol output low voltage (q) v cc = 5v, i ol = 2.1ma 0.4 v v cc < 4.5v, i ol = 100 m a 0.2 v v oh output high voltage (q) v cc = 5v, i oh = C400 m a 2.4 v v cc < 4.5v, i oh = C100 m av cc C 0.2 v table 5a. dc characteristics for m93sx6 version (t a = 0 to 70 c, C40 to 85 c or C40 to 125 c; v cc = 4.5v to 5.5v) 3/24 m93s66, M93S56, m93s46
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc , q in hi-z 1 m a i cc supply current (read) v cc = 5v, s = v ih , f = 1 mhz 1 ma v cc = 2.5v, s = v ih , f = 1 mhz 0.75 ma supply current (write, erase) v cc = 5v, s = v ih , f = 1 mhz 1.5 ma v cc = 2.5v, s = v ih , f = 1 mhz 1 ma i cc1 supply current (standby) v cc = 5v, s = v ss , c = v ss , w = v ss or v cc , pre = v ss or v cc 40 m a v cc = 2.5v, s = v ss , c = v ss , w = v ss or v cc , pre = v ss or v cc 10 m a v il input low voltage (d, c, s, w, pre) C0.3 0.25 v cc v v ih input high voltage (d, c, s, w, pre) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5v, i ol = 2.1ma 0.2 v cc v v cc < 4.5v, i ol = 100 m a 0.2 v v oh output high voltage (q) v cc = 5v, i oh = C400 m a 0.8 v cc v v cc < 4.5v, i oh = C100 m av cc C 0.2 v table 5b. dc characteristics for m93sx6-w version (t a = 0 to 70 c or C40 to 85 c; v cc = 2.5v to 5.5v) within the memory, an user defined area may be protected against further write instructions. the size of this area is defined by the content of a protect register, located outside of the memory array. as a final protection step, data may be per- manently protected by programming a one time programming bit (otp bit) which locks the protect register content. programming is internally self-timed (the external clock signal on c input may be disconnected or left running after the start of a write cycle) and does not require an erase cycle prior to the write instruc- tion. the write instruction writes 16 bits at one time into one of the 256/128/64 words of the m93s46/s56/s66 respectively, the page write in- struction writes up to 4 words of 16 bits to sequen- tial locations, assuming in both cases that all addresses are outside the write protected area. after the start of the programming cycle, a ready/busy signal is available on the data output (q) when chip select (s) is driven high. an internal feature of the m93sx6 provides power- on data protection by inhibiting any operation when the supply is too low. the design of the m93sx6 and the high endurance cmos technol- ogy used for its fabrication give an erase/write cycle endurance of 1,000,000 cycles and a data retention of 40 years. description (contd) 4/24 m93s66, M93S56, m93s46
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc , q in hi-z 1 m a i cc supply current (read) v cc = 5v, s = v ih , f = 1 mhz 1 ma v cc = 2.5v, s = v ih , f = 1 mhz 0.75 ma v cc = 1.8v, s = v ih , f = 1 mhz 0.75 ma supply current (write, erase) v cc = 5v, s = v ih , f = 1 mhz 1.5 ma v cc = 2.5v, s = v ih , f = 1 mhz 1 ma v cc = 1.8v, s = v ih , f = 1 mhz 1 ma i cc1 supply current (standby) v cc = 5v, s = v ss , c = v ss , w = v ss or v cc , pre = v ss or v cc 40 m a v cc = 2.5v, s = v ss , c = v ss , w = v ss or v cc , pre = v ss or v cc 10 m a v cc = 1.8v, s = v ss , c = v ss , w = v ss or v cc , pre = v ss or v cc 5 m a v il input low voltage (d, c, s, w, pre) C0.3 0.3 v cc v v ih input high voltage (d, c, s, w, pre) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5v, i ol = 2.1ma 0.2 v cc v v cc < 4.5v, i ol = 100 m a 0.2 v v oh output high voltage (q) v cc = 5v, i oh = C400 m a 0.8 v cc v v cc < 4.5v, i oh = C100 m av cc C 0.2 v table 5c. dc characteristics for m93sx6-r version (t a = 0 to 70 c or C40 to 85 c; v cc = 1.8v to 5.5v) 5/24 m93s66, M93S56, m93s46
symbol alt parameter test condition min max unit t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t shch t css chip select high to clock high 50 ns t clsh t sks clock low to chip select high 100 ns t dvch t dis input valid to clock high 100 ns t chdx t dih clock high to input transition 100 ns t chql t pd0 clock high to output low 500 ns t chqv t pd1 clock high to output valid 500 ns t clprx t preh clock low to protect enable transition 0ns t slwx t peh chip select low to write enable transition 250 ns t clsl t csh clock low to chip select low 0 ns t slch chip select low to clock high 250 ns t slsh t cs chip select low to chip select high note 1 250 ns t shqv t sv chip select high to output valid 500 ns t slqz t df chip select low to output hi-z note 3 500 ns t chcl t skh clock high to clock low note 2 250 ns t clch t skl clock low to clock high note 2 250 ns t w t wp erase/write cycle time 10 ms f c f sk clock frequency v cc min 0 1 mhz notes: 1. chip select must be brought low for a minimum of t slsh between consecutive instructions cycles. 2. the clock frequency specification calls for a minimum clock period of 1/f c , therefore the sum of the timings t chcl +t clch must be greater or equal to 1/f c . for example, if t chcl is 250ns, then t clch must be at least 750ns for f c =1mhz. 3. characterized but not 100% tested. table 6a. ac characteristics for m93sx6, m93sx6-w, m93sx6-r versions (t a = 0 to 70 c or C40 to 85 c; v cc = 4.5v to 5.5v) 6/24 m93s66, M93S56, m93s46
symbol alt parameter test condition min max unit t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t shch t css chip select high to clock high 100 ns t clsh t sks clock low to chip select high 100 ns t dvch t dis input valid to clock high 50 ns t chdx t dih clock high to input transition 50 ns t chql t pd0 clock high to output low 250 ns t chqv t pd1 clock high to output valid 250 ns t clprx t preh clock low to protect enable transition 0ns t slwx t peh chip select low to write enable transition 250 ns t clsl t csh clock low to chip select low 0 ns t slch chip select low to clock high 250 ns t slsh t cs chip select low to chip select high note 1 250 ns t shqv t sv chip select high to output valid 250 ns t slqz t df chip select low to output hi-z note 3 200 ns t chcl t skh clock high to clock low note 2 200 ns t clch t skl clock low to clock high note 2 200 ns t w t wp erase/write cycle time 10 ms f c f sk clock frequency v cc min 0 1 mhz notes: 1. chip select must be brought low for a minimum of t slsh between consecutive instructions cycles. 2. the clock frequency specification calls for a minimum clock period of 1/f c , therefore the sum of the timings t chcl +t clch must be greater or equal to 1/f c . for example, if t chcl is 250ns, then t clch must be at least 750ns for f c =1mhz. 3. characterized but not 100% tested. table 6b. ac characteristics for m93sx6-w, m93sx6-r versions (t a = 0 to 70 c or C40 to 85 c; v cc = 2.5v) 7/24 m93s66, M93S56, m93s46
symbol alt parameter test condition min max unit t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t shch t css chip select high to clock high 100 ns t clsh t sks clock low to chip select high 100 ns t dvch t dis input valid to clock high 100 ns t chdx t dih clock high to input transition 100 ns t chql t pd0 clock high to output low 500 ns t chqv t pd1 clock high to output valid 500 ns t clprx t preh clock low to protect enable transition 0ns t slwx t peh chip select low to write enable transition 250 ns t clsl t csh clock low to chip select low 0 ns t slch chip select low to clock high 250 ns t slsh t cs chip select low to chip select high note 1 250 ns t shqv t sv chip select high to output valid 500 ns t slqz t df chip select low to output hi-z note 3 300 ns t chcl t skh clock high to clock low note 2 250 ns t clch t skl clock low to clock high note 2 250 ns t w t wp erase/write cycle time 10 ms f c f sk clock frequency v cc min 0 1 mhz notes: 1. chip select must be brought low for a minimum of t slsh between consecutive instructions cycles. 2. the clock frequency specification calls for a minimum clock period of 1/f c , therefore the sum of the timings t chcl +t clch must be greater or equal to 1/f c . for example, if t chcl is 250ns, then t clch must be at least 750ns for f c =1mhz. 3. characterized but not 100% tested. table 6c. ac characteristics for m93sx6-r version (t a = 0 to 70 c or C40 to 85 c; v cc = 1.8v) 8/24 m93s66, M93S56, m93s46
symbol alt parameter test condition min max unit t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t shch t css chip select high to clock high 50 ns t clsh t sks clock low to chip select high 100 ns t dvch t dis input valid to clock high 100 ns t chdx t dih clock high to input transition 100 ns t chql t pd0 clock high to output low 500 ns t chqv t pd1 clock high to output valid 500 ns t clprx t preh clock low to protect enable transition 0ns t slwx t peh chip select low to write enable transition 250 ns t clsl t csh clock low to chip select low 0 ns t slch chip select low to clock high 250 ns t slsh t cs chip select low to chip select high note 1 250 ns t shqv t sv chip select high to output valid 500 ns t slqz t df chip select low to output hi-z note 3 300 ns t chcl t skh clock high to clock low note 2 250 ns t clch t skl clock low to clock high note 2 250 ns t w t wp erase/write cycle time 10 ms f c f sk clock frequency v cc min 0 1 mhz notes: 1. chip select must be brought low for a minimum of t slsh between consecutive instructions cycles. 2. the clock frequency specification calls for a minimum clock period of 1/f c , therefore the sum of the timings t chcl +t clch must be greater or equal to 1/f c . for example, if t chcl is 250ns, then t clch must be at least 750ns for f c =1mhz. 3. characterized but not 100% tested. table 6d. ac characteristics for m93sx6 version (t a = C40 to 125 c; v cc = 4.5v to 5.5v) 9/24 m93s66, M93S56, m93s46
pre w c s d op code op code start start op code input tchdx tdvch tclsh tclch tchcl twvch tprvch ai02025 tshch figure 4. synchronous timing, start and op-code input power-on data protection in order to prevent data corruption and inadvertent write operations during power-up and power-down, a power on reset (por) circuit resets all internal programming circuitry and sets the device in the write disable mode. C at power-up and power-down, the device must not be selected (that is, the s input must be driven low) until the supply voltage reaches the operating value vcc specified in the ac and dc tables. C when v cc reaches its functional value, the de- vice is properly reset (in the write disable mode) and is ready to decode and execute an incoming instruction. below the power on reset threshold voltage, the m93sx6 is in reset mode. for the m93sx6 specified at 5v, the por threshold voltage is around 3v. for all the other m93sx6 specified at low v cc (with -w and -r v cc range options), the por threshold voltage is around 1.5v. 10/24 m93s66, M93S56, m93s46
figure 5. synchronous timing, read or write ai002026 c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15 q0 pre w c s d hi-z tw tdvch ai02027 q tclprx tslwx tclsl tchdx tslsh tslqz busy tshqv ready write cycle address/data input an a0/d0 tslch 11/24 m93s66, M93S56, m93s46
instructions the m93s66/s56/s46 have eleven instructions, as shown in table 7. each instruction is preceded by the rising edge of the signal applied on the chip select (s) input (assuming that the clock c is low). after the device is selected, the internal logic waits for the start bit, which define the begining of the instruction bit stream. the start bit is the first 1 read on d input during the rising edge of the clock c. following the start bit, the op-codes of the instruc- tions are made up of the 2 following bits. notice that some instructions use only these first two bits, others use also the first two bits of the address to define the op-code. the op-code is then followed by the address of the word to be accessed. for the m93s46, the address is made up of 6 bits (see table 7a). for the M93S56 and m93s66, the address is made up of 8 bits (see table 7b). the m93sx6 is fabricated in cmos technology and is therefore able to run from zero hz (static input signals) up to the maximum ratings (specified in table 6). instr. description w pre start bit op- code address (1) data req. clock cycles additional information read read data from memory x 0 1 10 a5-a0 q15-q0 write write data to memory 1 0 1 01 a5-a0 d15-d0 25 write is executed if the address is not inside the protected area pawrite page write to memory 1 0 1 11 a5-a0 n x d15-d0 9 + n x 16 write is executed if all the n addresses are not inside the protected area wrall write all memory 1 0 1 00 01xxxx d15-d0 25 write all data if the protect register is cleared wen write enable 1 0 1 00 11xxxx 9 wds write disable x 0 1 00 00xxxx 9 prread protect register read x 1 1 10 xxxxxx q5-q0 + flag data output = protect register content + protect flag bit prwrite protect register write 1 1 1 01 a5-a0 9 data above specified address a5-a0 are protected prclear protect register clear 1 1 1 11 111111 9 protect flag is also cleared (cleared flag = 1) pren protect register enable 1 1 1 00 11xxxx 9 prds protect register disable 1 1 1 00 000000 9 otp bit is set permanently note: 1. x = dont care bit. table 7a. instruction set for the m93s46 12/24 m93s66, M93S56, m93s46
instr. description w pre start bit op- code address (1,2) data req. clock cycles additional information read read data from memory x 0 1 10 a7-a0 q15-q0 write write data to memory 1 0 1 01 a7-a0 d15-d0 27 write is executed if the address is not inside the protected area pawrite page write to memory 1 0 1 11 a7-a0 n x d15-d0 11 + n x 16 write is executed if all the n addresses are not inside the protected area wrall write all memory 1 0 1 00 01xxxxxx d15-d0 27 write all data if the protect register is cleared wen write enable 1 0 1 00 11xxxxxx 11 wds write disable x 0 1 00 00xxxxxx 11 prread protect register read x 1 1 10 xxxxxxxx q7-q0 + flag data output = protect register content + protect flag bit prwrite protect register write 1 1 1 01 a7-a0 11 data above specified address a7-a0 are protected prclear protect register clear 1 1 1 11 11111111 11 protect flag is also cleared (cleared flag = 1) pren protect register enable 1 1 1 00 11xxxxxx 11 prds protect register disable 1 1 1 00 00000000 11 otp bit is set permanently notes: 1. x = dont care bit. 2. address bit a7 is not decoded by the M93S56. table 7b. instruction set for the M93S56 and m93s66 13/24 m93s66, M93S56, m93s46
read the read instruction (read) outputs serial data on the data output (q). when a read instruction is received, the instruction and address are de- coded and the data from the memory is transferred into an output shift register. a dummy 0 bit is output first followed by the 16 bit word with the msb first. output data changes are triggered by the low to high transition of the clock (c). the m93sx6 will automatically increment the address and will clock out the next word as long as the chip select input (s) is held high. in this case the dummy 0 bit is not output between words and a continuous stream of data can be read. write enable and write disable the write enable instruction (wen) authorizes the following write instructions to be executed. the write disable instruction (wds) disables the exe- cution of the following write instructions and the internal programming cycle cannot run. when power is first applied, the m93sx6 is in write disable mode and all write instructions are inhib- ited. when the wen instruction is executed, write instructions remain enabled until a write disable instruction (wds) is executed or v cc falls below the power-on reset threshold voltage. to protect the memory contents from accidental corruption, it is advisable to issue the wds instruc- tion after every write cycle. the read instruction is not affected by the wen or wds instructions. write the write instruction (write) is composed of the start bit plus the op-code followed by the address and the 16 data bits to be written. the write enable signal (w) must be held high during the write instruction. data input (d) is sampled on the low to high transition of the clock. after the last data bit has been sampled, chip select (s) must be brought low before the next rising edge of the clock (c) in order to start the self-timed programming cycle. this is really important as, if s is brought low before or after this specific frame window, the addressed location will not be programmed, provid- ing that the address in not in the protected area. if the m93sx6 is still performing the write cycle, the busy signal (q = 0) will be returned if the chip select input (s) is driven high after the t slsh delay, and the m93sx6 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the m93sx6 is ready to receive a new instruction. programming is internally self-timed (the external clock signal on c input may be disconnected or left running after the start of a write cycle). page write a page write instruction (pawrite) contains the first address to be written followed by up to 4 data words. the write enable signal (w) must be held high during the pawrite instruction. input ad- dress and data are sampled on the low to high transition of the clock. after the receipt of each data word, bits a1-a0 of the internal address register are incremented, the high order bits (ax-a2) remaining unchanged. users must take care by software to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over. after the lsb of the last data word, chip select (s) must be brought low before the next rising edge of the clock (c) in order to start the self-timed program- ming cycle. this is really important as, if s is brought low before or after this specific frame win- dow, the addressed locations will not be pro- grammed. the page write operation will not be performed if any of the 4 words is addressing the protected area. if the m93sx6 is still performing the programming cycle, the busy signal (q = 0) will be returned if the chip select input (s) is driven high, and the m93sx6 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the m93sx6 is ready to receive a new instruction. write all the write all instruction (wrall) is valid only after the protect register has been cleared by executing a prclear (protect register clear) instruction. the write all instruction simultaneously writes the whole memory with the same data word included in the instruction. the write enable signal (w) must be held high before and during the write all instruc- tion. input address and data are sampled on the low to high transition of the clock. if the m93sx6 is still performing the write cycle, the busy signal (q = 0) will be returned if the chip select input (s) is driven high after the t slsh delay, and the m93sx6 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the m93sx6 is ready to receive a new instruction. ready/busy status during every programming cycle (after a write, wrall or pawrite instruction) the data output (q) indicates the ready/busy status of the memory when the chip select is driven high. once the m93sx6 is ready, the data output is set to 1 until a new start bit is decoded or the chip select is brought low. 14/24 m93s66, M93S56, m93s46
memory write protection and protect register the m93sx6 offers a protect register containing the bottom address of the memory area which has to be protected against write instructions. in addi- tion to this protect register, two flag bits are used to indicate the protect register status: the protect flag enabling/disabling the memory protection throught the protect register and the otp bit which, when set, disables access to the protect register and thus prevents any further modifica- tions of this protect register value. the content of the protect register is defined when using the prwrite instruction, it may be read when using the prread instruction. a specific instruction pren (protect register enable) allows the user to execute the protect instructions prclear, prwrite and prds. this pren instruction being used together with the signals applied on the input pins pre (protect register enable) and w (write enable). accessing the protect register is done by execut- ing the following sequence: C wen: execute the write enable instruction, C pren: execute the pren instruction, C prwrite, prclear or prds: the protection then may be defined, in terms of size of the protected area (prwrite, prclear) and may be set permanently (prds instruction). protect register read the protect register read instruction (prread) outputs on the data output q the content of the protect register, followed by the protect flag bit. the protect register enable pin (pre) must be driven high before and during the instruction. as in the read instruction a dummy 0 bit is output first. since it is not possible to distinguish if the protect register is cleared (all 1s) or if it is written with all 1s, user must check the protect flag status (and not the protect register content) to ascertain the setting of the memory protection. protect register enable the protect register enable instruction (pren) is used to authorize the use of further prclear, prwrite and prds instructions. the pren insruction does not modify the protect flag bit value. note: a write enable (wen) instruction must be executed before the protect enable instruction. both the protect enable (pre) and write enable (w) input pins must be held high during the instruc- tion execution. protect register clear the protect register clear instruction (prclear) clears the address stored in the protect register to all 1s, and thus enables the execution of write and wrall instructions. the protect register clear execution clears the protect flag to 1. both the protect enable (pre) and write enable (w) input pins must be driven high during the instruc- tion execution. note: a pren instruction must immediately pre- cede the prclear instruction. protect register write the protect register write instruction (prwrite) is used to write into the protect register the ad- dress of the first word to be protected. after the prwrite instruction execution, all memory loca- tions equal to and above the specified address, are protected from writing. the protect flag bit is set to 0, it can be read with protect register read instruction. both the protect enable (pre) and write enable (w) input pins must be driven high during the instruction execution. note: a pren instruction must immediately pre- cede the prwrite instruction, but it is not neces- sary to execute first a prclear. protect register disable the protect register disable instruction sets the one time programmable bit (otp bit). the protect register disable instruction (prds) is a one time only instruction which latches the protect regis- ter content, this content is therefore unalterable in the future. both the protect enable (pre) and write enable (w) input pins must be driven high during the instruction execution. the otp bit cannot be directly read, it can be checked by reading the content of the protect register (prread instruc- tion), then by writing this same value into the pro- tect register (prwrite instruction): when the otp bit is set, the ready/busy status cannot ap- pear on the data output (q). when the otp bit is not set, the busy status appear on the data output (q). note: a pren instruction must immediately pre- cede the prds instruction. 15/24 m93s66, M93S56, m93s46
ai00889d 1 1 0 an a0 qn q0 data out d s q s write addr op code 1 0an a0 data in d q op code dn d0 1 busy ready s write enable 1 0xnx0 d op code 1 01 s write disable 1 0xnx0 d op code 0 0 0 check status addr pre read pre w pre w pre figure 6. read, write, wen, wds sequences notes: 1. an - xn - qn - dn: refer to table 7a for the m93s46. 2. an - xn - qn - dn: refer to table 7b for the M93S56 and m93s66. 16/24 m93s66, M93S56, m93s46
ai00890c s page write 1 1an a0 data in d q op code dn d0 1 busy ready check status addr pre w s write all 1 0xnx0 data in d q op code dn d0 0 busy ready check status addr pre w 01 figure 7. pawrite, wrall sequences notes: 1. an - xn - dn: refer to table 7a for the m93s46. 2. an - xn - dn: refer to table 7b for the M93S56 and m93s66. 17/24 m93s66, M93S56, m93s46
notes: 1. an - xn - dn: refer to table 7a for the m93s46. 2. an - xn - dn: refer to table 7b for the M93S56 and m93s66. ai00891d 1 1 0 xn x0 data out d s q s protect register write addr op code 1 0an a0 d q op code 1 busy ready s protect register enable 1 0xnx0 d op code 1 01 check status addr pre protect register read pre w pre w an a0 f f = protect flag figure 8. prread, prwrite, pren sequences 18/24 m93s66, M93S56, m93s46
notes: 1. an - xn - dn: refer to table 7a for the m93s46. 2. an - xn - dn: refer to table 7b for the M93S56 and m93s66. ai00892c s protect register clear 1 1 d q op code 1 busy ready check status addr pre w 111 s protect register disable 1 0 d q op code 0 busy ready check status addr pre w 000 figure 9. prclear, prds sequences 19/24 m93s66, M93S56, m93s46
ai01395 s an-1 c d write start d0 "1" "0" an glitch an-2 address and data are shifted by one bit figure 10. write sequence with one clock glitch common i/o operation the data output (q) and data input (d) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (a0) and the first data bit output by q. the reader should refer to the stmicroelectronics application note an394 "microwire eeprom common i/o operation". clock pulse counter the m93sx6 offers a functional security filtering glitches on the clock input (c), the clock pulse counter. in a normal environment, the m93sx6 expectes to receive the exact amount of data on the d input (start bit, op-code, address, data), that is the exact amount of clock pulses on the c input. in a noisy environment, the number of pulses received (on the clock input c) may be greater than the clock pulses delivered by the master (microcontroller) driving the m93sx6. in such a case, a part of the instruction is delayed by one bit (see figure 10), and it may induce an erroneous write of data at a wrong address. the m93sx6 has an on-chip counter which counts the clock pulses from the start bit until the falling edge of the chip select signal. for the write instructions with a M93S56 (or m93s66), the number of clock pulses incoming to the counter must be exactly 27 from the start bit to the falling edge of chip select signal (1 start bit + 2 op-code bit + 8 address bit + 16 data bit = 27): if so, the M93S56 (or m93s66) executes the write instruction. if the number of clock pulses is not equal to 27, the instruction will not be executed (and data will not be corrupted). the clock pulse counter is active on write, pawrite, wrall, prwrite and prclear in- structions. in order to determine the exact number of clock pulses needed for all the m93sx6 on write instructions, refer to tables 7a and 7b, in the column: requested clock cycles. 20/24 m93s66, M93S56, m93s46
ordering information scheme devices are shipped from the factory with the memory content set at all "1s" (ffffh). for a list of available options (operating voltage, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. memory density 66 4 kbit 56 2 kbit 46 1 kbit operating voltage blank 4.5v to 5.5v w 2.5v to 5.5v r 1.8v to 5.5v package bn psdip8 0.25mm frame mn so8 150mil width temperature range 1 (1) 0 to 70 c 6 C40 to 85 c 3 (2) C40 to 125 c option t tape & reel packing example: M93S56 C w mn 6 t notes: 1. temperature range on request only. 2. produced with high reliability certified flow (hrcf), in v cc range 4.5v to 5.5v at 1mhz only. 21/24 m93s66, M93S56, m93s46
psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b symb mm inches typ min max typ min max a 3.90 5.90 0.154 0.232 a1 0.49 C 0.019 C a2 3.30 5.30 0.130 0.209 b 0.36 0.56 0.014 0.022 b1 1.15 1.65 0.045 0.065 c 0.20 0.36 0.008 0.014 d 9.20 9.90 0.362 0.390 e 7.62 C C 0.300 C C e1 6.00 6.70 0.236 0.264 e1 2.54 C C 0.100 C C ea 7.80 C 0.307 C eb 10.00 0.394 l 3.00 3.80 0.118 0.150 n8 8 drawing is not to scale psdip8 - 8 pin plastic skinny dip, 0.25mm lead frame 22/24 m93s66, M93S56, m93s46
so-a e n cp b e a d c l a1 a 1 h h x 45? symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27C C0.050C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 drawing is not to scale so8 - 8 lead plastic small outline, 150 mils body width 23/24 m93s66, M93S56, m93s46
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 1997 stmicroelectronics - all rights reserved ? microwire is a registered trademark of national semiconductor corp. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 24/24 m93s66, M93S56, m93s46

▲Up To Search▲

Price & Availability of M93S56

	To Download M93S56 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .